In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, a reference clock signal of a given frequency is generated together with a number of different clock signals having the same frequency but with different phases. In one typical implementation, the different clock signals are generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase and frequency of an incoming data stream and one or more of the clock signals are selected for data recovery.
A number of existing digital CDR circuits use voltage controlled delay loops (VCDL) to generate a number of clocks having the same frequency and different phase for data sampling (i.e., oversampling). For example, published International Patent Application No. WO 97/14214, discloses a compensated delay locked loop timing vernier. Generally, the disclosed timing vernier produces a set of timing signals of similar frequency and evenly distributed phase. An input reference clock signal is passed through a succession of delay stages. A separate timing signal is produced at the output of each delay stage. The reference clock signal and the timing signal output of the last delay stage are compared by an analog phase lock controller. The analog phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock. Based on the results of the oversampled data, the internal clock is delayed so that it provides data sampling adjusted to the center of the “eye.” The phase of the VCDL is adjusted to keep up with phase deviations of the incoming data.
FIG. 1 illustrates the transitions in a data stream 100. As shown in FIG. 1, the data is “ideally” sampled in the middle between two transition points. The phases generated by the VCDL are adjusted to align with the transitions and sample points, respectively. Thus, the internal clock is typically delayed so that the data sampling is adjusted to the center of the “data eye,” in a known manner. Such uniformly spaced transition and data sampling clock phases are generally considered useful under “ideal” circumstances.
In practice, however, it may be desirable to position the data sampling position either earlier or later than the “ideal” transition and sample points. For example, in threshold-based Decision Feedback Equalization (DFE) it is desirable to move the data sampling position earlier. Likewise, in classical DFE implementations, transients in the intersymbol interference (ISI) correction circuitry may not settle by the time when the “ideal” data sampling clock phase is generated. Thus, for classical DFE implementations, it may be desirable to delay the data sampling phase clock by moving the data sampling position later.
A need therefore exists for methods and apparatus for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to “ideal” transition and sample points.